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negative terminal of the battery to the P side just makes the situation worse Hence, the PN junction conducts only a small leakage current, which is usually assumed to be negligible The diode is thus called reverse biased The PN junction then appears like a variable capacitance As the negative bias is increased, the junction thickness becomes greater and the capacitance decreases The diode is forward biased when the P material is connected to the positive terminal of the battery However, current still will not ow until the forward bias is high enough to overcome the internal electronic forces For silicon at room temperature this occurs when the external bias is 06 V As illustrated in Figure 162b, as the voltage increases above 06 V, the junction current increases rapidly PN junctions are used at low frequencies as recti er diodes for power supplies.

Neudeck, 'Fully Depleted Dual-Gated Thin-Film SOI p-MOSFET with an Isolated Polysilicon Backgate," Proc IEEE International SO1 Conf Oct 1995, p 135 14 P J Schubert and G W Neudeck, "Confined Lateral Selective Epitaxial Growth of Silicon for Device Fabrication," IEE, Electron Device Lett 11, 181 (1990) 15 S Venkatesan, C Subramanian, G W Neudeck, and J P Denton, "Thin-Film Siliconon-Insulator (SOI) Device Applications of Selective Epitaxial Overgrowth," Proc IEEE Int S01 Conf Oct 1993, p 76 16 B Aspar, C Pudda, A M Papon, A J Auberton-Herv6, and J M Lamure, "Ultra Thin Buried Oxide Layers Formed by Low 'Dose SIMOX Process," in S Cristoloveanu, ed, Silicon-on-Insulator Technology and Devices, The Electrochemical Society, Proceedings Vol 94-11, 1994, p 62, Abstract 541 17 A J Auberton-Herv6, J M Lamure, T Barge, M Bruel, B Aspar, and J L Pelloie, "SOI Materials for ULSI Applications,' Semiconduct Int 97 (Oct 1995) 18.

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For RF applications, the variable capacitance characteristic of the PN junction is used for electronic tuning of the PLO, as described in 17 Related semiconductor junctions used in RF devices are compared in Figure 163 The PN junction is shown in Figure 163a Figure 163b shows a Schottky junction, formed between a metallic conductor and an N-doped semiconductor When the metal and N-doped material are placed together, electrons from the N material are attracted to the metal and leave an insulating junction in the N material The characteristics of the Schottky junction are similar to those of the PN junction, except that the capacitance of the Schottky junction is reduced By special fabrication techniques, the Schottky junction begins to conduct when the bias voltage just becomes positive An ohmic junction is shown in Figure 163c.

The ohmic junction is used to make electrical connection to the N- or P-doped material If a metal conductor is connected directly to N-doped semiconductor material, a Schottky junction is created To make an electrical connection to the N material without any junction characteristics, an N region, which is a heavily doped semiconductor, is connected to the N region and the metal is connected to the N material The ohmic junction has no unique characteristics; current ows equally well in either direction with no capacitance effects The PIN diode (Fig 163d) is formed from P and N material with a thin layer of undoped or I type material between The I material reduces the capacitance in the reversed-bias case, and the PIN diode is used as an electronically controlled attenuator or an electronic switch..

R Stengl, T Tan, and U G6sele, "A Model for the Silicon Wafer Bonding Process," Jpn J Apple Phys 28, 1735 (1989) 19 T Abe, M Nakano, and T Itoh, "Silicon Wafer-Bonding Process Technology for SOI Structures," in D Schmidt, ed, Proc 4th Int Symp Silicon-on-InsulatorTechnology and Devices, The Electrochemical Society, Vol 90-6, 1990, p 61 20 S D Collins, "Etch Stop Techniques 'or Micromachining," J Electrochem Soc 144, 2242 (1997) 21 A Yamada, 0 Okabayashi, T Nakamura, E Kanda, and M Kawashima, "A Computer Controlled Polishing System for Silicon-on-Insulator (SOI)," Ext Abstr 5th Int Workshop on Future Electron Device3, Miyagi-Zao, Japan, May 1988, p 201 22 See, for example: Solid-State Technology, p 155, June 1994, or back cover page of European Semiconductor, May 1994 23 P B Mumola and G J.

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